Integrated circuit performance is being continually improved by increasing device switching speed, increasing interconnection density and reducing cross-talk between adjacent conductors. Switching speeds have been increased and cross-talk reduced by employing new dielectric thin film material having low dielectric constant, such as porous carbon-doped silicon dioxide. Interconnections have been increased by increasing the number of interconnected conductive layers and reducing feature size (e.g., line widths, hole diameters). Connecting between such deep layers entails high aspect ratio (deep and narrow) conductor openings or “vias”. Such fine features have required photoresist (for photolithography) adaptable to shorter wavelengths. Such photoresist tends to be thinner and more prone to form imperfections such as pin holes or striations during the dielectric etch process. This problem is addressed by employing a fluorocarbon chemistry during the plasma etch of the dielectric inter-layer insulation film, in order to deposit a protective fluorocarbon polymer on the photoresist. The polymer must be removed from the wafer after the etch process in order to avoid contaminating later process steps that must be performed on the wafer. Therefore, a post-etch polymer removal step is performed. However, in the post-etch polymer removal step, it is difficult to remove all of the deposited polymer. This is because some polymer penetrates through a gap between the wafer edge and a ring collar process kit at the wafer pedestal periphery, and accumulates on the wafer backside at the periphery. Such a gap is required to avoid interference with the electrostatic chuck (ESC) that forcibly clamps the wafer to a cooled surface to meet the temperature control requirements of the plasma etch process. The wafer edge-to-ring collar gap is too narrow for plasma to penetrate and remove the polymer from the wafer backside during the post-etch polymer removal step. Therefore, a conventional approach to this problem has been to employ an oxygen plasma in the post-etch polymer removal step, to oxidize carbon-containing materials (such as polymer and photoresist), followed by dipping the wafer in liquid HF acid. This step can employ a separate relatively inexpensive “ashing” chamber having a heated wafer support pedestal capable of relatively high wafer temperatures (e.g., 300 or more degrees) with a simple remote plasma source. This process does not harm a conventional dielectric material such as silicon dioxide, which is a strong material. However, such an oxidizing process does catastrophic harm to the newer low dielectric constant insulator materials such as porous carbon-doped silicon dioxide. The oxidizing chemistry of the post-etch clean step removes the carbon from the carbon-doped silicon dioxide dielectric material, the carbon eventually being replaced by water from the atmosphere. This greatly increases the dielectric constant of the insulator, removing its main advantage. Such damage is apparent as undercutting of the dielectric layer sidewalls viewed in a profile image. This undercutting is revealed upon dipping the wafer in dilute acid following the post-etch clean step. Another problem is that such an oxidizing process does not completely remove the backside polymer, even after 60 seconds, according to our investigation.
Therefore, what is needed is a way of completely and quickly removing polymer from the wafer backside that does not damage the low-dielectric constant insulator material without requiring any extra process time.